The invention relates to semiconductor processing, and more particularly to an improved method for forming a buried plate such as used in a trench capacitor of an advanced microelectronic device, e.g., a dynamic random access memory (DRAM).
A goal of the semiconductor industry is to increase the circuit density of integrated circuits (“ICs” or “chips”), most often by decreasing the size of individual devices and circuit elements of a chip. Trench capacitors are used in some types of DRAMs for storing data bits. Often, increasing the circuit density of such DRAMs requires reducing the size of the trench capacitor, which, in turn, requires reducing the area of the chip occupied by the trench capacitor. Achieving such reduction in surface area is not straightforward, because different components of the storage capacitor do not scale at the same rate, and some components cannot be scaled below a certain size. It would be desirable to provide a process of forming a trench capacitor which helps maintain the lateral dimensions of the trench capacitor within tolerances at the surface of the chip that are needed to achieve further reductions in size.
The fabrication of a trench capacitor begins by etching an opening in a semiconductor substrate. A trench capacitor is typically formed by a series of process steps, starting by etching a deep trench in a semiconductor region of a substrate. A patterned pad stack is generally provided on the substrate to define a window through which the opening is to be etched.
The trench capacitor is a plate capacitor, having as a first plate a “buried plate”, which is a charge-containing region in the semiconductor substrate adjacent to the sidewall of the trench. A second plate of the capacitor is provided as a “node electrode”, separated from the buried plate by a thin “node dielectric.” The buried plate is typically disposed adjacent to only a lower portion of the trench, while an isolation collar is provided in the upper portion of the trench to isolate the trench capacitor from other nearby devices such as transistors. The buried plate is typically formed by outdiffusion of dopants from a dopant source into the lower portion. Typically, the dopant source is one that provides dopants, such as arsenic-doped silicate oxide, i.e., arsenic-doped glass (ASG). The dopant source is deposited to cover the sidewalls and bottom of the trench, such as through a low-pressure chemical vapor deposition (LPCVD) process. Thereafter, an annealing process is conducted to drive the dopants into the adjacent areas of the substrate to form the buried plate.
Unfortunately, the conventional ASG process to form a buried plate is not ideal. First, the exposed region of the semiconductor substrate adjacent to the upper portion of the trench may be undesirably doped when the dopant source layer is not completely sealed. Second, the exposed region of the semiconductor substrate adjacent to the upper portion of the trench may be undesirably oxidized and widened when the formed oxide is removed. These problems are illustrated with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a stage in the formation of a buried plate for a trench capacitor according to a prior art process. As shown in FIG. 1, a trench 105 is vertically etched into the semiconductor substrate 100 through an opening 115 in a pad stack 130 and through an opening in an overlying hard mask layer (not shown) that is removed after etching the trench. The sidewall 110 of the trench represents the edge of the semiconductor substrate, as stands after first etching the trench 105, before subsequent processes are performed. Illustratively, a layer 112 of ASG is deposited onto the sidewall 110 and bottom 145 of the trench 105 as a source of dopant material for later forming the buried plate. A cap layer 200, typically consisting essentially of undoped silicon dioxide, is then deposited over the ASG layer 112. A fill material (not shown), such as a photoresist material, is then typically deposited and recessed to expose the cap layer 200 and the ASG layer 112 in the upper portion of the trench. The exposed cap layer 200 and the ASG layer 112 are then removed from the upper portion 180 of the trench sidewall 110, while the cap layer 200 and the ASG layer 112 remain in place along the lower portion 170 of the trench sidewall 110, as well as the bottom of the trench 105. The fill material may then be removed from the trench. Hereinafter, references to the trench sidewall 110 and lower portion 170 include the trench bottom 145, as well. As apparent from FIG. 1, after the foregoing processing, the top surface 160 of the ASG layer is exposed, in proximity to the upper portion 180 of the trench sidewall 110. This arrangement adversely affects the results of subsequent annealing to form the buried plate.
Thereafter, the substrate 100 is placed in a chamber containing oxygen and annealed for the purpose of driving the arsenic dopant into the substrate 100 adjacent to the lower portion 170 of the trench sidewall to form a buried plate 102, as shown in FIG. 2. During the annealing, a region 155 of the semiconductor substrate adjacent to the original trench sidewall 110 becomes oxidized, such that the lower portion 170 of the trench sidewall 110 is now at a widened location 130 relative to the original trench sidewall 110. This is a desirable result, because a widened trench along the lower portion 170 results in a larger surface area of the trench capacitor (not shown) to be completed by later processing, such larger surface area directly contributing to higher capacitance.
However, referring to FIG. 2, disadvantageous results occur along the upper portion 180 of the trench sidewall 110 as a byproduct of annealing in the oxygen-containing chamber. Along the upper portion 180, the semiconductor substrate is oxidized in region 150. The oxidized region 150 extends outwardly from the original trench sidewall 110 to a post-oxidation sidewall 140, such region which typically is at least as thick as the oxide region 155, and may be even thicker than oxide region 155. The widening of the upper portion 180 of the trench is undesirable, because it negatively impacts overlay tolerance for subsequent processing. In addition, the exposed top surface 160 of the ASG layer shown in FIG. 1 results in the arsenic dopant outdiffusing during the annealing process into region 190 of the semiconductor substrate 100 in the vicinity of the upper portion 180 of the trench sidewall. The undesired doped region 190 of the substrate is shown in FIG. 2 adjacent to the oxidized region 150, which in turn is disposed along the upper portion 180 of the trench sidewall 110. Doping the semiconductor region 190 disposed along the upper trench portion 180 is undesirable because it increases the leakage current of a transistor to be subsequently formed along the upper trench portion and negatively impacts its performance.
FIG. 3 illustrates a further stage in fabrication, after subsequent processing has been performed to remove the oxidized semiconductor material that has formed in regions 150 and 155 shown in FIG. 2. The trench with widened upper portion 180 is further illustrated in FIG. 3 as an increase in a lateral dimension 310, as measured by the spacing bounded by the post-oxidation trench sidewall 140. This increased dimension 310 is shown in relation to the original lateral dimension 305 of the trench, as represented by the original location 210 of the trench sidewall.
The two problems of trench widening and diffusion of arsenic into the substrate adjacent to the upper portion of the trench negatively impact the performance of the trench capacitor and subsequently formed transistor, and the ability to maintain process tolerances. Both problems are due to exposure of the semiconductor substrate along the upper portion of the trench sidewall to oxygen and to the dopant source material (e.g., ASG) during annealing. Accordingly, a new processing method is desired to address the foregoing concerns.